1. Field of Invention
This invention relates to a cascade A/D converter with error correction that is error free; and more particulary, to such converter that prevents generation of errors due to noise.
2. Description of the Prior Art
A/D converters include those which are of small scale, low power consumption and low input capacity. This type of converter uses a single clock and provides high speed operation. However, there is a problem of error generation in such converters. The inventors had disclosed in Japan Unexamined Application SN 9/238,077 (1997), a cascade A/D converter which uses a single clock and is operable without errors. Such a device is described in FIG. 1, which shows a cascade 5-bit A/D converter that outputs an alternate binary code (also called "gray" code). The device comprises comparators 8a-8d; latch circuits 9a-9e; D/A converters 10a-10c; subtractors 11a-11c; comparators 13a-13h; logical product circuits (called "AND circuits") 14-17; exclusive logical sum circuits (called "EOR circuits") 18-20; logical sum circuits (called "OR circuits") 21-23; and AND circuits 24, 25. Analog input signal 100a and digital output signal 101a are provided as shown.
Comparators 13a,3b and AND circuit 14 comprise window comparator 50a. Comparators 13c, 13d and AND circuit 15 comprise window comparator 50b. comparators 13e,13f and AND circuit 16 comprise window comparator 50c. Comparators 13g, 13h and AND circuit 17 comprise window comparator 50d. OR circuits 21-23 and and circuits 24,25 comprise error correction circuit 51.
Analog input signal 100a is applied to each non-inverted input terminal of comparators 8a and 13a, inverted input terminal of comparator 13b and the addition input terminal of subtractor 11a. The output terminal of comparator 8a is connected to latch circuit 9a, D/A converter 10a, and one input terminal of EOR circuit 18. The output terminal of D/A converter 10a is connected to the subtraction input terminal of subtractor 11a. The output terminal of comparators 13a and 13b are connected to the input terminals of AND circuit 14. The output terminal of AND circuit 14 is connected to one input terminal of OR circuit 21 and to the negative logic input terminals of AND circuits 15-17, 24 and 25.
The output terminal of subtractor 11a is connected to each noninverted input terminal of comparators 8b and 13c, inverted input terminal of comparator 13d and the addition input terminal of subtractor 11b. The output terminal of comparator 8b is connected to D/A converter 10b, the other input terminal of EOR circuit 18, and one input terminal of EOR circuit 19. The output terminal of D/A converter 10b is connected to the subtraction input terminal of subtractor 11b. Each output terminal of comparators 13c and 13d is connected to the other two positive logic input terminals of AND circuit 15, respectively. The output terminal of AND logic circuit 15 is connected to one input terminal of OR circuit 22 and each of the negative logic input terminals of AND circuits 16,17 and 25. The output terminal of EOR circuit 18 is connected to the other input terminal of OR circuit 21. The output terminal of OR circuit 21 is connected to the latch circuit 9b.
The output terminal of subtractor 11b is connected to each non-inverted input terminal of comparators 8c and 13e, the inverted input terminal of comparator 13f, and the addition input terminal of subtractor 11c. The output terminal of comparator 8c is connected to D/A converter 10c, the other input terminal of EOR circuit 19, and one input terminal of EOR circuit 20. The output terminal of EOR circuit 19 is connected to the other input terminal of OR circuit 22. The output terminal of OR circuit 22 is connected to the positive logic input terminal of AND circuit 24. The output terminal of AND circuit 24 is connected to latch circuit 9c. Each output terminal of comparators 13e and 13f is connected to the other two positive logic input terminals of AND circuit 16, respectively. The output terminal of AND circuit 16 is connected to one input terminal of OR circuit 23 and the negative logic input terminal of AND circuit 17. The output terminal of subtractor 11c is connected to the non-inverted input terminals of comparators 8d and 13g and the inverted input terminal of comparator 13h.
The output terminal of comparator 8d is connected to the other input terminal of EOR circuit 20. The output terminal of EOR circuit 20 is connected to the other input terminal of OR circuit 23. The output terminal of OR circuit 23 is connected to the positive logic input terminal of AND circuit 25. The output terminal of AND circuit 25 is connected to the latch circuit 9d. Each output terminal of comparators 13g and 13h is connected to the other two positive logic input terminals of AND circuit 17, respectively. The output terminal of AND circuit 17 is connected to latch circuit 9e. The output terminal of latch circuit 9a-9e are used to output digital output signal 101a.
The inverted input terminals of comparators 8a-8d are grounded. The voltages of +.DELTA.V is applied to the non-inverted input terminals of comparators 13b,13d,13f, and 13h. The voltages of -.DELTA.V is applied to the inverted input terminals of comparators 13a,13c,13e and 13g, respectively. However, .DELTA.V=FS/32, wherein FS=full scale.
Operation of the device of FIG. 1 will now be described with refference to FIGS. 2 and 3, which show characteristic curves that indicate each output or each input for analog input signal 10a from -FS/2 to +FS/2. In FIGS. 2 and 3, lines (a) to (d) show the outputs of comparators 8a-8d; lines (e) to (h) show the outputs of window comparators 50a to 50d; lines (i) to (k) show the outputs of EOR circuits 18-20; and lines (l) to (p) show the inputs to latch circuits 9a-9e, respectively.
Comparators 8a-8d judge the zero crossing of analog input signal 100a, the output of subtractor 11a, the output of subtractor 11b, and the output of subtactor 11c, respectively.
Each of window comparators 50a-50d outputs a "high level" signal when the input signal is in each vicinity of "zero" and the output of the window comparator at the preceding stage is at a "low level" signal. Hence, window comparator 50a outputs a "high level" signal when analog input signal 100a is in each vicinity of "zero" as shown in line (e) of FIG. 2.
Window comparator 50b can output a "high level" signal when analog input signal 100a is in each vicinity of "zero" and "+FS/4" as shown in line (b) of FIG. 2. However, since the output signal from window comparator 50a, at the preceding stage is at a "high level" when analog input signal 100a is in each vicinity of "zero", window comparator 50b output "high level" signals only in each vicinity of "+FS/4" as shown in line (f) of FIG. 2.
Window comparator 50c can output a "high level" signal in seven positions as shown in line (c) of FIG. 2. However, since the positions where window comparator 50a or 50b at the previous states outputs a "high level" signal, are rejected, the output of window comparator 50c is of the waveform shown in line (g) of FIG. 2. Similarly, window comparator 50d can output a "high level" signal in 15 positions, as shown iin line (d) of FIG. 2. However, since the positions where window comparator 50a, 50b, or 50c at the previous stages outputs a "high level" signal are rejected, the output of window comparator 50d is of the waveform shown in line (h) of FIG. 2.
The output signals from EOR circuit 18-20 comprise "gray codes" of intermediate bits in digital output signal 101a; but, it is known that the output signals generate spike like noise as shown in lines (i)-(k) of FIG. 3. This is caused because the changes of signals from "high level" to "low level" or from "low level" to "high level" are not steep. Error correction circuit 51 rejects or eliminates the spike like noise as shown in lines (m)-(o) of FIG. 3, by correcting the portions where the spike like noise is generated using the output signals from the window comparators 50a-50d. That is, the spike like noise, shown in lines (i)-(k) of FIG. 3 is eliminated or rejected by masking with the output signal from window comparator 50a, the output signals from window Comparators 50a,50b, and the output signals from window comparators 50a, 50b, and 50c, respectively.
The output signals from window comparators 50a-50c act to change to "high level" in a certain region (called "window width") near the code changing points to establish all the lower codes. Considering the first stage window comparator 50a, the second bit is forced to a "high level" and the third bit, fourth bit and the least significant bit (LSB) which is the fifth bit are forced to "low level" near the changing point for the most significant bit (MSB).
The window widths for establishing each bit are not required to be essentially the same. As shown in line (m) of FIG. 3, the region in which the second bit is changed to "high level" can be up to a half of a full scale. As shown in line (n) of FIG. 3, a region of up to 1/4 of the full scale can be allowed for the third bit. The allowable window width becomes narrower as the bit becomes lower and at the least significant bit (LSB) as shown in line (p) of FIG. 3, the upper limit of window width becomes 1/16 of the full scale, or 2 LSB.
However, since window comparator 50a that detects the changing points for MSB propagates its output to the lower bits, the window width must be constant. For example, the window width for making the second bit at a "high level" at the MSB changing point must be the same as the window width for carrying the LSB to a "low level" Accordingly, a problem arises when the window width comes near the noise level with high resolution, namely, that an error is generated in the code of the second bit where the window comparator 50a malfunctions due to noise.